1. Field of the Invention
The present invention relates to a semiconductor memory apparatus, and verify read method and system, and more particularly, to an apparatus, a method, and a system of performing a memory read by using statistical distribution.
2. Discussion of the Related Art
A demand for a non-volatile memory that requires low power consumption, a small dimension, a high speed, and high reliability has increased with propagation of mobile devices. An existing charge storage type non-volatile memory (NVM) has been in accord with such a specification while reducing the size of a device with the development of semiconductor process technology. However, in recent years, a new memory has been actively researched while memory process technology has experienced difficulties in reducing the size of the device. At preset, resistive type memories primarily including a phase charge random access memory (PCRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), and the like attract public attentions, which distinguish data by using a resistance change. The resistive type memories have advantages including high integrity, a high switching speed, low power consumption, and the like. However, since the resistive type memories have a wide distribution of resistance values, the resistive type memories have a difficulty in distinguishing data. Due to various elements including disturbance associated with reading and writing of neighboring cells, a change in resistance value depending on a temperature and time, a change in resistance value depending on repeated reading/writing operations as well as such a difficulty, a probability in failing to distinguishing data is increased when the data is distinguished based on a predetermined reference.
In order to overcome the difficulties, a research into a method of reading data by using a variable reference in a resistive change memory has been made in recent years (see U.S. patent Registration No. 7,495,984).
FIG. 1 is a diagram for describing a method of generating a reference in the related art. As illustrated in FIG. 1, U.S. patent Registration No. 7,495,984 mentions that when a reference is generated by using a plurality of cells which is positioned in the same block where a cell to be sensed is positioned, a midpoint reference can be generated by using some cells and a reference voltage is generated by using cells in a memory array, and as a result, a local change of a resistance value can be reflected. However, it is difficult to determine that such a reference is a reference to correctly distinguish all cells in an array block in which a voltage of the midpoint reference generated by using just some cells is significantly high due to a characteristic of the resistive type memory having a large distribution. For example, if Rmax of FIG. 1 has a smallest value in a high resistive state (HRS) (data “0”) distribution and Rmin also has the smallest value in a low resistive state (LRS) (data “1”) distribution, a reference voltage generated herein generates a reference which is inclined toward the LRS, and as a result, a probability in failing to sensing LRS cells having a relatively higher resistive distribution is increased.